| @@ -51,9 +51,6 @@ class CPU extends MultiIOModule { | |||||
| testHarness.currentPC := IF.testHarness.PC | testHarness.currentPC := IF.testHarness.PC | ||||
| /** | |||||
| TODO: Your code here | |||||
| */ | |||||
| // Stage 1 | // Stage 1 | ||||
| IFBarrier.in := IF.io | IFBarrier.in := IF.io | ||||
| @@ -79,10 +79,6 @@ class Decoder() extends Module { | |||||
| SRLI -> List(N, Y, N, N, Y, N, N, branchType.DC, ITYPE, ALUOps.SRL), | SRLI -> List(N, Y, N, N, Y, N, N, branchType.DC, ITYPE, ALUOps.SRL), | ||||
| SLL -> List(N, Y, N, N, N, N, N, branchType.DC, ImmFormat.DC, ALUOps.SLL), | SLL -> List(N, Y, N, N, N, N, N, branchType.DC, ImmFormat.DC, ALUOps.SLL), | ||||
| SLLI -> List(N, Y, N, N, Y, N, N, branchType.DC, ITYPE, ALUOps.SLL), | SLLI -> List(N, Y, N, N, Y, N, N, branchType.DC, ITYPE, ALUOps.SLL), | ||||
| /** | |||||
| TODO: Fill in the blanks | |||||
| */ | |||||
| ) | ) | ||||
| @@ -18,9 +18,6 @@ class InstructionDecode extends MultiIOModule { | |||||
| val io = IO( | val io = IO( | ||||
| new Bundle { | new Bundle { | ||||
| /** | |||||
| * TODO: Your code here. | |||||
| */ | |||||
| val instruction = Input(new Instruction) | val instruction = Input(new Instruction) | ||||
| val writeEnable = Input(UInt(32.W)) | val writeEnable = Input(UInt(32.W)) | ||||
| val writeAddr = Input(UInt(32.W)) | val writeAddr = Input(UInt(32.W)) | ||||
| @@ -46,9 +43,6 @@ class InstructionDecode extends MultiIOModule { | |||||
| testHarness.testUpdates := registers.testHarness.testUpdates | testHarness.testUpdates := registers.testHarness.testUpdates | ||||
| /** | |||||
| * TODO: Your code here. | |||||
| */ | |||||
| decoder.instruction := io.instruction | decoder.instruction := io.instruction | ||||
| registers.io.readAddress1 := io.instruction.registerRs1 | registers.io.readAddress1 := io.instruction.registerRs1 | ||||
| @@ -13,14 +13,6 @@ class InstructionFetch extends MultiIOModule { | |||||
| ) | ) | ||||
| /** | |||||
| * TODO: Add input signals for handling events such as jumps | |||||
| * TODO: Add output signal for the instruction. | |||||
| * The instruction is of type Bundle, which means that you must | |||||
| * use the same syntax used in the testHarness for IMEM setup signals | |||||
| * further up. | |||||
| */ | |||||
| val io = IO( | val io = IO( | ||||
| new Bundle { | new Bundle { | ||||
| val PC = Output(UInt()) | val PC = Output(UInt()) | ||||
| @@ -41,12 +33,6 @@ class InstructionFetch extends MultiIOModule { | |||||
| testHarness.PC := IMEM.testHarness.requestedAddress | testHarness.PC := IMEM.testHarness.requestedAddress | ||||
| /** | |||||
| * TODO: Your code here. | |||||
| * | |||||
| * You should expand on or rewrite the code below. | |||||
| */ | |||||
| val addr = Mux(io.jumpEnable, io.jumpAddr, PC + 4.U) | val addr = Mux(io.jumpEnable, io.jumpAddr, PC + 4.U) | ||||
| when (io.jumpEnable) { | when (io.jumpEnable) { | ||||
| //printf(p"Jump to ${Hexadecimal(addr)}\n") | //printf(p"Jump to ${Hexadecimal(addr)}\n") | ||||