From 6879d00dc0775a16bd2b1223bbf37b862dae4ece Mon Sep 17 00:00:00 2001
From: Sindre Stephansen <sindre@sindrestephansen.com>
Date: Wed, 16 Oct 2019 23:37:34 +0200
Subject: [PATCH] Remove TODO comments

---
 src/main/scala/CPU.scala     |  3 ---
 src/main/scala/Decoder.scala |  4 ----
 src/main/scala/ID.scala      |  6 ------
 src/main/scala/IF.scala      | 14 --------------
 4 files changed, 27 deletions(-)

diff --git a/src/main/scala/CPU.scala b/src/main/scala/CPU.scala
index 3ed99da..defc20a 100644
--- a/src/main/scala/CPU.scala
+++ b/src/main/scala/CPU.scala
@@ -51,9 +51,6 @@ class CPU extends MultiIOModule {
   testHarness.currentPC  := IF.testHarness.PC
 
 
-  /**
-    TODO: Your code here
-    */
   // Stage 1
   IFBarrier.in := IF.io
 
diff --git a/src/main/scala/Decoder.scala b/src/main/scala/Decoder.scala
index 4d62546..c7f0ff5 100644
--- a/src/main/scala/Decoder.scala
+++ b/src/main/scala/Decoder.scala
@@ -79,10 +79,6 @@ class Decoder() extends Module {
     SRLI   -> List(N,        Y,        N,       N,        Y,         N,       N,    branchType.DC,   ITYPE,        ALUOps.SRL),
     SLL    -> List(N,        Y,        N,       N,        N,         N,       N,    branchType.DC,   ImmFormat.DC, ALUOps.SLL),
     SLLI   -> List(N,        Y,        N,       N,        Y,         N,       N,    branchType.DC,   ITYPE,        ALUOps.SLL),
-
-    /**
-      TODO: Fill in the blanks
-      */
     )
 
 
diff --git a/src/main/scala/ID.scala b/src/main/scala/ID.scala
index 1711be9..ced9fe0 100644
--- a/src/main/scala/ID.scala
+++ b/src/main/scala/ID.scala
@@ -18,9 +18,6 @@ class InstructionDecode extends MultiIOModule {
 
   val io = IO(
     new Bundle {
-      /**
-        * TODO: Your code here.
-        */
       val instruction = Input(new Instruction)
       val writeEnable = Input(UInt(32.W))
       val writeAddr = Input(UInt(32.W))
@@ -46,9 +43,6 @@ class InstructionDecode extends MultiIOModule {
   testHarness.testUpdates     := registers.testHarness.testUpdates
 
 
-  /**
-    * TODO: Your code here.
-    */
   decoder.instruction := io.instruction
 
   registers.io.readAddress1 := io.instruction.registerRs1
diff --git a/src/main/scala/IF.scala b/src/main/scala/IF.scala
index b545461..da8d6e7 100644
--- a/src/main/scala/IF.scala
+++ b/src/main/scala/IF.scala
@@ -13,14 +13,6 @@ class InstructionFetch extends MultiIOModule {
   )
 
 
-  /**
-    * TODO: Add input signals for handling events such as jumps
-
-    * TODO: Add output signal for the instruction.
-    * The instruction is of type Bundle, which means that you must
-    * use the same syntax used in the testHarness for IMEM setup signals
-    * further up.
-    */
   val io = IO(
     new Bundle {
       val PC = Output(UInt())
@@ -41,12 +33,6 @@ class InstructionFetch extends MultiIOModule {
   testHarness.PC := IMEM.testHarness.requestedAddress
 
 
-  /**
-    * TODO: Your code here.
-    *
-    * You should expand on or rewrite the code below.
-    */
-
   val addr = Mux(io.jumpEnable, io.jumpAddr, PC + 4.U)
   when (io.jumpEnable) {
     //printf(p"Jump to ${Hexadecimal(addr)}\n")