diff --git a/src/main/scala/Forwarder.scala b/src/main/scala/Forwarder.scala
index cbb09ce..f01ba0a 100644
--- a/src/main/scala/Forwarder.scala
+++ b/src/main/scala/Forwarder.scala
@@ -18,14 +18,24 @@ class Forwarder extends Module {
     val loadFreeze = Output(Bool())
   })
 
-  val exToRs1 = io.ID.instruction.registerRs1 === io.EX.instruction.registerRd && io.EX.controlSignals.regWrite
-  val exToRs2 = io.ID.instruction.registerRs2 === io.EX.instruction.registerRd && io.EX.controlSignals.regWrite
-  val memToRs1 = io.ID.instruction.registerRs1 === io.MEM.instruction.registerRd && io.MEM.controlSignals.regWrite
-  val memToRs2 = io.ID.instruction.registerRs2 === io.MEM.instruction.registerRd && io.MEM.controlSignals.regWrite
-  val wbToRs1 = io.ID.instruction.registerRs1 === io.WB.instruction.registerRd && io.WB.controlSignals.regWrite
-  val wbToRs2 = io.ID.instruction.registerRs2 === io.WB.instruction.registerRd && io.WB.controlSignals.regWrite
-  val ldToRs1 = exToRs1 && io.EX.controlSignals.memToReg
-  val ldToRs2 = exToRs2 && io.EX.controlSignals.memToReg
+  // Helper variables, to avoid long lines
+  val IDRs1 = io.ID.instruction.registerRs1
+  val IDRs2 = io.ID.instruction.registerRs2
+  val EXRd  = io.EX.instruction.registerRd
+  val MEMRd = io.MEM.instruction.registerRd
+  val WBRd  = io.WB.instruction.registerRd
+  val EXRegWrite  = io.EX.controlSignals.regWrite
+  val MEMRegWrite = io.MEM.controlSignals.regWrite
+  val WBRegWrite  = io.WB.controlSignals.regWrite
+
+  val exToRs1  = IDRs1 === EXRd  && IDRs1 =/= 0.U && EXRegWrite
+  val exToRs2  = IDRs2 === EXRd  && IDRs2 =/= 0.U && EXRegWrite
+  val memToRs1 = IDRs1 === MEMRd && IDRs1 =/= 0.U && MEMRegWrite
+  val memToRs2 = IDRs2 === MEMRd && IDRs2 =/= 0.U && MEMRegWrite
+  val wbToRs1  = IDRs1 === WBRd  && IDRs1 =/= 0.U && WBRegWrite
+  val wbToRs2  = IDRs2 === WBRd  && IDRs2 =/= 0.U && WBRegWrite
+  val ldToRs1  = exToRs1 && io.EX.controlSignals.memToReg
+  val ldToRs2  = exToRs2 && io.EX.controlSignals.memToReg
 
   io.loadFreeze := (ldToRs1 || ldToRs2)
 
@@ -56,7 +66,7 @@ class Forwarder extends Module {
 
   // If a value read from MEM is used as the address in the next instruction, forward it
   val memToMem = io.EX.instruction.registerRs2 === io.MEM.instruction.registerRd && io.EX.controlSignals.memWrite
-  val wbToMem = io.EX.instruction.registerRs2 === io.WB.instruction.registerRd && io.EX.controlSignals.memWrite
+  val wbToMem  = io.EX.instruction.registerRs2 === io.WB.instruction.registerRd  && io.EX.controlSignals.memWrite
 
   when (memToMem) {
     io.memWrite := io.writeback