Implement bitwise and shift operations

src/main/scala/Decoder.scala

@@ -8,7 +8,7 @@ import chisel3.util.ListLookup
   * This module is mostly done, but you will have to fill in the blanks in opcodeMap.
   * You may want to add more signals to be decoded in this module depending on your
   * design if you so desire.
-  * 
+  *
   * In the "classic" 5 stage decoder signals such as op1select and immType
   * are not included, however I have added them to my design, and similarily you might
   * find it useful to add more
@@ -36,12 +36,12 @@ class Decoder() extends Module {
   val Y = 1.asUInt(1.W)
 
   /**
-    * In scala we sometimes (ab)use the `->` operator to create tuples. 
+    * In scala we sometimes (ab)use the `->` operator to create tuples.
     * The reason for this is that it serves as convenient sugar to make maps.
-    * 
+    *
     * This doesn't matter to you, just fill in the blanks in the style currently
     * used, I just want to demystify some of the scala magic.
-    * 
+    *
     * `a -> b` == `(a, b)` == `Tuple2(a, b)`
     */
   val opcodeMap: Array[(BitPat, List[UInt])] = Array(
@@ -54,6 +54,22 @@ class Decoder() extends Module {
     ADD    -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       rs2,       ImmFormat.DC, ALUOps.ADD),
     ADDI   -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       imm,       ITYPE,        ALUOps.ADD),
     SUB    -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       rs2,       ImmFormat.DC, ALUOps.SUB),
+    AND    -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       rs2,       ImmFormat.DC, ALUOps.AND),
+    ANDI   -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       imm,       ImmFormat.DC, ALUOps.AND),
+    OR     -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       rs2,       ImmFormat.DC, ALUOps.OR),
+    ORI    -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       imm,       ImmFormat.DC, ALUOps.OR),
+    XOR    -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       rs2,       ImmFormat.DC, ALUOps.XOR),
+    XORI   -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       imm,       ImmFormat.DC, ALUOps.XOR),
+    SLT    -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       rs2,       ImmFormat.DC, ALUOps.SLT),
+    SLTI   -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       imm,       ImmFormat.DC, ALUOps.SLT),
+    SLTU   -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       rs2,       ImmFormat.DC, ALUOps.SLTU),
+    SLTIU  -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       imm,       ImmFormat.DC, ALUOps.SLTU),
+    SRA    -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       rs2,       ImmFormat.DC, ALUOps.SRA),
+    SRAI   -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       imm,       ImmFormat.DC, ALUOps.SRA),
+    SRL    -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       rs2,       ImmFormat.DC, ALUOps.SRL),
+    SRLI   -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       imm,       ImmFormat.DC, ALUOps.SRL),
+    SLL    -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       rs2,       ImmFormat.DC, ALUOps.SLL),
+    SLLI   -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       imm,       ImmFormat.DC, ALUOps.SLL),
 
     /**
       TODO: Fill in the blanks

src/main/scala/Execute.scala

@@ -26,13 +26,13 @@ class Execute extends Module {
     ALUOps.OR     -> (data1U | data2U),
     ALUOps.XOR    -> (data1U ^ data2U),
     // TODO: SLT. Set GPR?
-    //ALUOps.SLT    -> (data1S < data2S).asUInt,
-    //ALUOps.SLTU   -> (data1U < data2U),
-    //ALUOps.SLL    -> (data1S << data2U).asUInt,
-    //ALUOps.SRL    -> (data1S >> data2U).asUInt,
-    //ALUOps.SRA    -> (data1S >> data2U).asUInt, // TODO: SRA sign-extend?
-    //ALUOps.COPY_A -> (data1U),
-    //ALUOps.COPY_B -> (data2U),
+    ALUOps.SLT    -> (data1S < data2S).asUInt,
+    ALUOps.SLTU   -> (data1U < data2U),
+    ALUOps.SLL    -> (data1S << data2U(4, 0)).asUInt,
+    ALUOps.SRL    -> (data1U >> data2U).asUInt,
+    ALUOps.SRA    -> (data1S >> data2U).asUInt, // TODO: SRA sign-extend?
+    ALUOps.COPY_A -> (data1U),
+    ALUOps.COPY_B -> (data2U),
 
   )