From c451f113b879ac202041517b2e6af090995cfa3d Mon Sep 17 00:00:00 2001
From: Sindre Stephansen <sindre@sindrestephansen.com>
Date: Tue, 10 Sep 2019 16:54:40 +0200
Subject: [PATCH] Implement memory module

---
 src/main/scala/MEM.scala | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/MEM.scala b/src/main/scala/MEM.scala
index 0038a6d..ecdaaf9 100644
--- a/src/main/scala/MEM.scala
+++ b/src/main/scala/MEM.scala
@@ -18,6 +18,11 @@ class MemoryFetch() extends MultiIOModule {
 
   val io = IO(
     new Bundle {
+      val dataIn         = Input(UInt(32.W))
+      val dataAddress    = Input(UInt(32.W))
+      val writeEnable    = Input(Bool())
+
+      val dataOut        = Output(UInt(32.W))
     })
 
 
@@ -35,7 +40,9 @@ class MemoryFetch() extends MultiIOModule {
   /**
     * Your code here.
     */
-  DMEM.io.dataIn      := 0.U
-  DMEM.io.dataAddress := 0.U
-  DMEM.io.writeEnable := false.B
+  DMEM.io.dataIn      := io.dataIn
+  DMEM.io.dataAddress := io.dataAddress
+  DMEM.io.writeEnable := io.writeEnable
+
+  io.dataOut := DMEM.io.dataOut
 }