Extend the pipeline

src/main/scala/CPU.scala

@@ -32,6 +32,8 @@ class CPU extends MultiIOModule {
   val MEM = Module(new MemoryFetch)
   // val WB  = Module(new Execute) (You may not need this one?)
 
+  val data1 = RegInit(UInt(32.W), 0.U)
+  val data2 = RegInit(UInt(32.W), 0.U)
 
   /**
     * Setup. You should not change this code
@@ -56,9 +58,15 @@ class CPU extends MultiIOModule {
     */
   ID.io.PC := IF.io.PC
   ID.io.instruction := IF.io.instruction
+  ID.io.regWriteData := EX.io.result
+  data1 := ID.io.data1
+  data2 := ID.io.data2
+
+  MEM.io.dataIn := 0.U
+  MEM.io.dataAddress := 0.U
+  MEM.io.writeEnable := false.B
 
   EX.io.ALUop := ID.io.ALUop
-  EX.io.data1 := ID.io.data1
-  EX.io.data2 := ID.io.data2
-  ID.io.regWriteData := EX.io.result
+  EX.io.data1 := data1
+  EX.io.data2 := data2
 }

src/main/scala/Execute.scala

@@ -12,6 +12,8 @@ class Execute extends Module {
       val result = Output(UInt(32.W))
     })
 
+  val result = RegInit(UInt(32.W), 0.U)
+
   val data1S = io.data1.asSInt
   val data2S = io.data2.asSInt
   val data1U = io.data1.asUInt
@@ -31,11 +33,14 @@ class Execute extends Module {
     //ALUOps.SRA    -> (data1S >> data2U).asUInt, // TODO: SRA sign-extend?
     //ALUOps.COPY_A -> (data1U),
     //ALUOps.COPY_B -> (data2U),
+
   )
 
-  io.result := MuxLookup(
+  result := MuxLookup(
     io.ALUop,
     0.U(32.W),
     ALUopMap,
   )
+
+  io.result := result
 }

src/main/scala/ID.scala

@@ -35,6 +35,22 @@ class InstructionDecode extends MultiIOModule {
   val registers = Module(new Registers)
   val decoder   = Module(new Decoder).io
 
+  val data1 = RegInit(UInt(32.W), 0.U)
+  val data2 = RegInit(UInt(32.W), 0.U)
+  val ALUop = RegInit(UInt(4.W), 0.U)
+  val controlSignals = Reg(new ControlSignals)
+
+  // The data will be written back in 4 cycles,
+  // so we move the data between registers while we wait
+  class RegInput extends Bundle {
+    val writeEnable = Bool()
+    val writeAddress = UInt(32.W)
+  }
+
+  val regInput0 = Reg(new RegInput)
+  val regInput1 = Reg(new RegInput)
+  val regInput2 = Reg(new RegInput)
+
 
   /**
     * Setup. You should not change this code
@@ -51,27 +67,36 @@ class InstructionDecode extends MultiIOModule {
 
   registers.io.readAddress1 := io.instruction.registerRs1
   registers.io.readAddress2 := io.instruction.registerRs2
-  registers.io.writeEnable  := decoder.controlSignals.regWrite
-  registers.io.writeAddress := io.instruction.registerRd
+  registers.io.writeEnable  := regInput2.writeEnable
+  registers.io.writeAddress := regInput2.writeAddress
   registers.io.writeData    := io.regWriteData
 
-  io.controlSignals := decoder.controlSignals
-  io.ALUop := decoder.ALUop
-  io.data1 := 0.U
-  io.data2 := 0.U
+  ALUop := decoder.ALUop
+  io.ALUop := ALUop
+  controlSignals := decoder.controlSignals
+  io.controlSignals := controlSignals
+
+  io.data1 := data1
+  io.data2 := data2
+
+
+  regInput0.writeEnable := decoder.controlSignals.regWrite
+  regInput0.writeAddress := io.instruction.registerRd
+  regInput1 := regInput0
+  regInput2 := regInput1
 
   switch (decoder.op1Select) {
     is (Op1Select.rs1) {
-      io.data1 := registers.io.readData1
+      data1 := registers.io.readData1
     }
     is (Op1Select.PC) {
-      io.data1 := io.PC
+      data1 := io.PC
     }
   }
 
   switch (decoder.op2Select) {
     is (Op2Select.rs2) {
-      io.data2 := registers.io.readData2
+      data2 := registers.io.readData2
     }
     is (Op2Select.imm) {
       val immTypeMap = Array(
@@ -83,7 +108,7 @@ class InstructionDecode extends MultiIOModule {
         ImmFormat.SHAMT -> 0.S, // TODO: Implement SHAMT
       )
 
-      io.data2 := MuxLookup(
+      data2 := MuxLookup(
         decoder.immType,
         0.S,
         immTypeMap,