From 793f78f2dea4d0a99ba8ef628fc367db6c5fa38a Mon Sep 17 00:00:00 2001
From: Sindre Stephansen <sindre@sindrestephansen.com>
Date: Fri, 22 Nov 2019 15:58:11 +0100
Subject: [PATCH] Implement proper jumping

---
 src/main/scala/Barriers.scala |  9 +++------
 src/main/scala/CPU.scala      | 28 ++++++++++++++++------------
 src/main/scala/IF.scala       | 11 +++--------
 3 files changed, 22 insertions(+), 26 deletions(-)

diff --git a/src/main/scala/Barriers.scala b/src/main/scala/Barriers.scala
index ba4b5f2..448bb18 100644
--- a/src/main/scala/Barriers.scala
+++ b/src/main/scala/Barriers.scala
@@ -43,7 +43,6 @@ class Barrier[B <: Bundle](b: B) extends MultiIOModule {
 
 class IFBundle extends Bundle {
   val PC          = UInt(32.W)
-  val next        = UInt(32.W)
   val instruction = new Instruction
 }
 
@@ -51,7 +50,6 @@ class IFBundle extends Bundle {
 class IFBarrier extends Barrier(new IFBundle) {
   out.instruction := barrier(in.instruction, false)
   out.PC          := barrier(in.PC)
-  out.next        := barrier(in.next)
 }
 
 
@@ -89,14 +87,13 @@ class MEMBundle extends Bundle {
   val controlSignals = new ControlSignals
   val result         = UInt(32.W)
   val dataOut        = UInt(32.W)
+  val branch         = Bool()
 }
 
 
 class MEMBarrier extends Barrier(new MEMBundle) {
-  out.PC             := barrier(in.PC)
-  out.instruction    := barrier(in.instruction)
-  out.controlSignals := barrier(in.controlSignals)
-  out.result         := barrier(in.result)
+  default()
+
   out.dataOut        := barrier(in.dataOut, false)
 }
 
diff --git a/src/main/scala/CPU.scala b/src/main/scala/CPU.scala
index 113b1d5..c5faa56 100644
--- a/src/main/scala/CPU.scala
+++ b/src/main/scala/CPU.scala
@@ -78,7 +78,7 @@ class CPU extends MultiIOModule {
 
   // Stage 1
   IFBarrier.in := IF.io
-  IF.io.addr   := IFBarrier.out.next
+  IF.io.addr   := IFBarrier.out.PC + 4.U
 
   // Stage 2
   ID.io.instruction            := IFBarrier.out.instruction
@@ -147,7 +147,9 @@ class CPU extends MultiIOModule {
     rs2 := IDBarrier.out.reg2
   }
 
-  //printf(p"0x${Hexadecimal(IF.io.PC)}: Reg write: ${MEMBarrier.out.controlSignals.regWrite}, ExToR1: $exToRs1, MEMToR1: $memToRs1, wbToR1: $wbToRs1, R1: $rs1, EX: ${EXBarrier.out.result}, MEM: ${MEMBarrier.out.dataOut}, WB: ${WBBarrier.out.writeback}}\n")
+  //printf(p"0x${Hexadecimal(IFBarrier.out.PC)}: next: ${Hexadecimal(IF.io.addr)} freeze: $freeze, ID imm: ${IDBarrier.out.imm}, ID PC: ${IDBarrier.out.PC}, EX result: ${EXBarrier.out.result}\n")
+
+  //printf(p"0x${Hexadecimal(IF.io.PC)}: Reg write: ${MEMBarrier.out.controlSignals.regWrite}, ExToR1: $exToRs1, MEMToR1: $memToRs1, wbToR1: $wbToRs1, R1: $rs1, ID: ${IDBarrier.out.imm.asUInt} EX: ${EXBarrier.out.result}, MEM: $writeback, WB: ${WBBarrier.out.writeback}}\n")
 
   //printf(p"0x${Hexadecimal(IF.io.PC)}: Next: 0x${Hexadecimal(IFBarrier.out.next)}, freeze: $freeze, IF: ${IFBarrier.out.instruction}, ID: ${IDBarrier.out.instruction}, EX: ${EXBarrier.out.instruction}, MEM: ${MEMBarrier.out.instruction}\n")
 
@@ -172,18 +174,22 @@ class CPU extends MultiIOModule {
   MEM.io.writeEnable           := EXBarrier.out.controlSignals.memWrite
   MEM.io.dataAddress           := EXBarrier.out.result
 
-  when (EXBarrier.out.branch) {
-    //IF.io.addr := EXBarrier.out.result
-  }
-
   MEMBarrier.in.PC             := EXBarrier.out.PC
   MEMBarrier.in.instruction    := EXBarrier.out.instruction
   MEMBarrier.in.controlSignals := EXBarrier.out.controlSignals
   MEMBarrier.in.result         := EXBarrier.out.result
+  MEMBarrier.in.branch         := EXBarrier.out.branch
   MEMBarrier.in.dataOut        := MEM.io.dataOut
 
   // Stage 5
-  when (freeze) {
+  when (EXBarrier.out.branch) {
+    IF.io.addr := EXBarrier.out.result
+    //printf(p"Jumping to ${EXBarrier.out.result}\n")
+    IDBarrier.clear := true.B
+    EXBarrier.clear := true.B
+  }
+
+  when (false.B && freeze) {
     ID.io.writeEnable         := false.B
     ID.io.writeAddr           := 0.U
     ID.io.writeData           := 0.U
@@ -198,13 +204,11 @@ class CPU extends MultiIOModule {
   WBBarrier.in.controlSignals := MEMBarrier.out.controlSignals
   WBBarrier.in.writeback      := writeback
 
-  writeback                   := MEMBarrier.out.result
-
   when (MEMBarrier.out.controlSignals.memToReg) {
     writeback := MEMBarrier.out.dataOut
-  }
-
-  when (MEMBarrier.out.controlSignals.jump) {
+  }.elsewhen (MEMBarrier.out.controlSignals.jump) {
     writeback := MEMBarrier.out.PC + 4.U
+  }.otherwise {
+    writeback := MEMBarrier.out.result
   }
 }
diff --git a/src/main/scala/IF.scala b/src/main/scala/IF.scala
index ef455a1..1f0941b 100644
--- a/src/main/scala/IF.scala
+++ b/src/main/scala/IF.scala
@@ -17,13 +17,12 @@ class InstructionFetch extends MultiIOModule {
     new Bundle {
       val PC = Output(UInt())
       val instruction = Output(new Instruction)
-      val next = Output(UInt(32.W))
 
       val addr = Input(UInt(32.W))
     })
 
   val IMEM = Module(new IMEM)
-  val PC   = WireInit(UInt(32.W), 0.U)
+  val PC   = WireInit(UInt(32.W), io.addr)
 
   /**
     * Setup. You should not change this code
@@ -33,19 +32,15 @@ class InstructionFetch extends MultiIOModule {
 
   IMEM.io.instructionAddress := PC
 
-  PC := io.addr
-
-  io.PC := RegNext(PC)
-  io.next := PC + 4.U
+  io.PC := PC
   io.instruction := IMEM.io.instruction.asTypeOf(new Instruction)
 
 
   /**
     * Setup. You should not change this code.
     */
-  when(testHarness.IMEMsetup.setup) {
+  when(testHarness.IMEMsetup.setup || RegNext(testHarness.IMEMsetup.setup)) {
     PC := 0.U
-    io.next := 0.U
     io.instruction := Instruction.NOP
   }
 }