diff --git a/src/main/scala/Barriers.scala b/src/main/scala/Barriers.scala
index ec99bc1..ba4b5f2 100644
--- a/src/main/scala/Barriers.scala
+++ b/src/main/scala/Barriers.scala
@@ -51,7 +51,7 @@ class IFBundle extends Bundle {
 class IFBarrier extends Barrier(new IFBundle) {
   out.instruction := barrier(in.instruction, false)
   out.PC          := barrier(in.PC)
-  out.next        := Mux(freeze, RegNext(in.next), in.next)
+  out.next        := barrier(in.next)
 }
 
 
diff --git a/src/main/scala/IF.scala b/src/main/scala/IF.scala
index dec0ded..ef455a1 100644
--- a/src/main/scala/IF.scala
+++ b/src/main/scala/IF.scala
@@ -23,8 +23,7 @@ class InstructionFetch extends MultiIOModule {
     })
 
   val IMEM = Module(new IMEM)
-  val PC   = RegInit(UInt(32.W), 0.U)
-
+  val PC   = WireInit(UInt(32.W), 0.U)
 
   /**
     * Setup. You should not change this code
@@ -32,12 +31,11 @@ class InstructionFetch extends MultiIOModule {
   IMEM.testHarness.setupSignals := testHarness.IMEMsetup
   testHarness.PC := IMEM.testHarness.requestedAddress
 
-
   IMEM.io.instructionAddress := PC
 
   PC := io.addr
 
-  io.PC := PC
+  io.PC := RegNext(PC)
   io.next := PC + 4.U
   io.instruction := IMEM.io.instruction.asTypeOf(new Instruction)
 
@@ -47,6 +45,7 @@ class InstructionFetch extends MultiIOModule {
     */
   when(testHarness.IMEMsetup.setup) {
     PC := 0.U
+    io.next := 0.U
     io.instruction := Instruction.NOP
   }
 }