diff --git a/src/main/scala/CPU.scala b/src/main/scala/CPU.scala
index ceb014d..360fc1c 100644
--- a/src/main/scala/CPU.scala
+++ b/src/main/scala/CPU.scala
@@ -66,7 +66,7 @@ class CPU extends MultiIOModule {
   //printf(p"S3: ALUop=${ID.io.ALUop}, data1=${ID.io.data1.asSInt}, data2=${ID.io.data2.asSInt} || ")
 
   // Stage 4
-  MEM.io.dataIn := 0.U
+  MEM.io.dataIn := ShiftRegister(ID.io.data3, 1)
   MEM.io.dataAddress := EX.io.result
   MEM.io.writeEnable := ShiftRegister(ID.io.controlSignals.memWrite, 1)
   //printf(p"S4: res=${EX.io.result} || ")
diff --git a/src/main/scala/ID.scala b/src/main/scala/ID.scala
index 5729ecc..dd27e6e 100644
--- a/src/main/scala/ID.scala
+++ b/src/main/scala/ID.scala
@@ -30,6 +30,7 @@ class InstructionDecode extends MultiIOModule {
       val controlSignals = Output(new ControlSignals)
       val data1 = Output(UInt(32.W))
       val data2 = Output(UInt(32.W))
+      val data3 = Output(UInt(32.W))
       val ALUop = Output(UInt(4.W))
     }
   )
@@ -39,6 +40,7 @@ class InstructionDecode extends MultiIOModule {
 
   val data1 = RegInit(UInt(32.W), 0.U)
   val data2 = RegInit(UInt(32.W), 0.U)
+  val data3 = RegInit(UInt(32.W), 0.U)
   val ALUop = RegInit(UInt(4.W), 0.U)
   val controlSignals = Reg(new ControlSignals)
 
@@ -69,6 +71,9 @@ class InstructionDecode extends MultiIOModule {
 
   io.data1 := data1
   io.data2 := data2
+  io.data3 := data3
+
+  data3 := registers.io.readData2
 
   switch (decoder.op1Select) {
     is (Op1Select.rs1) {