image/svg+xml
1
Reg_A
1
output
Reg_A
HDL
HDL
Circuit description
Simulator
Reg_A
1
output
Scala code
Word
Worder
Reg_A
1
output
Chisel graph
Chisel graph builder
Synthesizer
Reg_A
3
output 3
DataIn
dataIn
dataOut
Simulator
Synthesizer
FPGA
Compiler errors
Build errors