Removed solution. Yes I know it's in the commit history..

src/main/scala/DotProd.scala

@@ -23,17 +23,7 @@ class DotProd(val elements: Int) extends Module {
   val accumulator = RegInit(UInt(32.W), 0.U)
   val product = io.dataInA * io.dataInB
 
-
-  /**
-    * LF
-    */
-  when(counter.inc()){
-    io.outputValid := true.B
-    accumulator    := 0.U
-  }.otherwise{
-    io.outputValid := false.B
-    accumulator    := accumulator + product
-  }
-
-  io.dataOut := accumulator + product
+  // placeholder
+  io.dataOut := 0.U
+  io.outputValid := false.B
 }

src/main/scala/MatMul.scala

@@ -18,15 +18,7 @@ class MatMul(val rowDimsA: Int, val colDimsA: Int) extends MultiIOModule {
 
   val debug = IO(
     new Bundle {
-      val ready        = Output(Bool())
-      val dpValid      = Output(Bool())
-
-      val rowSelA      = Output(UInt(32.W))
-      val rowSelB      = Output(UInt(32.W))
-      val colSel       = Output(UInt(32.W))
-
-      val ma2dp        = Output(UInt(32.W))
-      val mb2dp        = Output(UInt(32.W))
+      val myDebugSignal = Output(Bool())
     }
   )
 
@@ -38,75 +30,22 @@ class MatMul(val rowDimsA: Int, val colDimsA: Int) extends MultiIOModule {
   val matrixB     = Module(new Matrix(rowDimsA, colDimsA)).io
   val dotProdCalc = Module(new DotProd(colDimsA)).io
 
-  // matrixA.dataIn      := 0.U
-  // matrixA.rowIdx      := 0.U
-  // matrixA.colIdx      := 0.U
-  // matrixA.readEnable  := false.B
-
-  // matrixB.rowIdx      := 0.U
-  // matrixB.colIdx      := 0.U
-  // matrixB.dataIn      := 0.U
-  // matrixB.readEnable  := false.B
-
-  // dotProdCalc.dataInA := 0.U
-  // dotProdCalc.dataInB := 0.U
-
-  // io.dataOut := 0.U
-  // io.outputValid := false.B
-
-
-
-  /**
-    * LF
-    */
-
-
-  // Get the data in
-  val ready = RegInit(false.B)
-
-  val (colCounter, colCounterWrap) = Counter(true.B, colDimsA)
-  val (rowSelA, rowSelAWrap)       = Counter(colCounterWrap, rowDimsA)
-  val (rowSelB, _)                 = Counter(rowSelAWrap & ready, rowDimsA * colDimsA)
-
-  when(!ready){
-    ready := rowSelAWrap
-    matrixA.readEnable := true.B
-    matrixB.readEnable := true.B
-
-    matrixA.colIdx := colCounter
-    matrixA.rowIdx := rowSelA
-
-    matrixB.colIdx := colCounter
-    matrixB.rowIdx := rowSelA
-
-  }.otherwise{
-    matrixA.readEnable := false.B
-    matrixB.readEnable := false.B
-
-    matrixA.colIdx := colCounter
-    matrixA.rowIdx := rowSelB
-
-    matrixB.colIdx := colCounter
-    matrixB.rowIdx := rowSelA
-  }
-
-
-  matrixA.dataIn := io.dataInA
-  matrixB.dataIn := io.dataInB
+  matrixA.dataIn      := 0.U
+  matrixA.rowIdx      := 0.U
+  matrixA.colIdx      := 0.U
+  matrixA.readEnable  := false.B
 
-  dotProdCalc.dataInA := matrixA.dataOut
-  dotProdCalc.dataInB := matrixB.dataOut
+  matrixB.rowIdx      := 0.U
+  matrixB.colIdx      := 0.U
+  matrixB.dataIn      := 0.U
+  matrixB.readEnable  := false.B
 
-  io.dataOut     := dotProdCalc.dataOut
-  io.outputValid := dotProdCalc.outputValid & ready
+  dotProdCalc.dataInA := 0.U
+  dotProdCalc.dataInB := 0.U
 
-  debug.ready        := ready
-  debug.dpValid      := dotProdCalc.outputValid
-  debug.rowSelA      := rowSelA
-  debug.rowSelB      := rowSelB
-  debug.colSel       := colCounter
+  io.dataOut := 0.U
+  io.outputValid := false.B
 
-  debug.ma2dp        := matrixA.dataOut
-  debug.mb2dp        := matrixB.dataOut
 
+  debug.myDebugSignal := false.B
 }

src/main/scala/Matrix.scala

@@ -32,22 +32,4 @@ class Matrix(val rowsDim: Int, val colsDim: Int) extends Module {
     rows(ii).readEnable := false.B
     rows(ii).idx        := 0.U
   }
-
-
-  /**
-    * LF
-    */
-  for(ii <- 0 until rowsDim){
-
-    rows(ii).dataIn := io.dataIn
-    rows(ii).idx    := io.colIdx
-
-    when(ii.U === io.rowIdx){
-      rows(ii).readEnable := io.readEnable
-    }.otherwise{
-      rows(ii).readEnable := false.B
-    }
-  }
-  io.dataOut := rows(io.rowIdx).dataOut
-
 }

src/main/scala/Tile.scala

@@ -1,2 +0,0 @@
-
-

src/main/scala/Vector.scala

@@ -24,13 +24,4 @@ class Vector(val elements: Int) extends Module {
 
   // placeholder
   io.dataOut := 0.U
-
-
-  /**
-    * LF
-    */
-  io.dataOut := contents(io.idx)
-  when(io.readEnable){
-    contents(io.idx) := io.dataIn
-  }
 }