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@@ -1,3 +1,4 @@ |
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#+LATEX_HEADER: \usepackage{minted} |
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* Writing chisel |
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** Prerequisites |
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+ *You should have some idea of how digital logic circuits work.* |
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@@ -247,7 +248,7 @@ |
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using testOnly <TAB> |
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Running the test should look something like this. |
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#+begin_src |
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#+begin_src text |
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sbt:chisel-module-template> testOnly Examples.MyIncrementTest |
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Run starting. Expected test count is: 0 |
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... |
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@@ -355,7 +356,7 @@ |
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Which can yield two different circuits depending on the opSel argument: |
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True: |
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[[./Images/ScalaCond1.png]] |
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#+begin_src |
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#+begin_src text |
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. |
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. |
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. |
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@@ -591,13 +592,13 @@ |
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} |
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#+end_src |
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#+begin_src |
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#+begin_src text |
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sbt:chisel-module-template> compile:test |
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... |
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#+end_src |
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As promised, this code compiles, but when you run the test which actually builds a simulator you |
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get the following: |
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#+begin_src |
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#+begin_src text |
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[success] Total time: 3 s, completed Apr 25, 2019 3:15:15 PM |
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... |
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sbt:chisel-module-template> testOnly Examples.InvalidSpec |
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@@ -617,7 +618,7 @@ |
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#+end_src |
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While scary, the actual error is only this line: |
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#+begin_src |
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#+begin_src text |
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firrtl.passes.CheckInitialization$RefNotInitializedException: @[Example.scala 25:21:@20.4] : [module Invalid] Reference myVec is not fully initialized. |
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: myVec.io.idx <= VOID |
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#+end_src |
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@@ -693,7 +694,7 @@ |
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In order to make it extra clear the Driver has the optional "verbose" parameter set to true. |
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This yields the following: |
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#+begin_src |
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#+begin_src text |
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DelaySpec: |
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SimpleDelay |
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... |
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@@ -819,7 +820,7 @@ |
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As it turns out printf can be rather misleading when using stateful circuits. |
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To see this in action, try running ~testOnly Examples.EvilPrintfSpec~ which yields the following |
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#+begin_src |
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#+begin_src text |
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In cycle 0 the output of counter is: 0 |
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according to printf output is: 0 |
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[info] [0.003] |
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