Øving 0 implemented

.gitignore

@@ -320,6 +320,8 @@ lib_managed/
 src_managed/
 project/boot/
 project/plugins/project/
+.ensime
+.ensime_cache/
 
 # Scala-IDE specific
 .scala_dependencies
@@ -337,3 +339,5 @@ project/plugins/project/
 
 # virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
 hs_err_pid*
+
+*.fir

TODOs.org

@@ -1,6 +1,9 @@
 * Thoughts
   For RISC-V bruk SODOR, finn på chisel sia
   
+* Doing
+  Finn ut hvordan bundles, defs etc burde fungere.
+  
 * Now
 ** TODO Port Babby to chisel3
 *** DONE compile and run
@@ -40,3 +43,5 @@
 *** Kombiner til en parametriserbar matrise, med medfølgende tester.
 *** Instansier to matriser
 *** Multipliser dem
+    
+    

ov0/project/build.properties

@@ -0,0 +1 @@
+sbt.version = 1.1.0

src/main/scala/Tile.scala → ov0/src/main/scala/Tile.scala

@@ -53,6 +53,32 @@ class myTest(c: Tile) extends PeekPokeTester(c) {
 
 }
 
-object Util {
+object Extras {
   def somefun(someval: Int) : Unit = {}
+
+  val vecA = List(1,  2, 4)
+  val vecB = List(2, -3, 1)
+
+  val dotProductForLoop = {
+    var dotProduct = 0
+    for(i <- 0 until vecA.length){
+      dotProduct = dotProduct + (vecA(i) * vecB(i))
+    }
+    dotProduct
+  }
+
+
+  // If you prefer a functional style scala has excellent support.
+  val dotProductFP = (vecA zip vecB)
+    .map{ case(a, b) => a*b }
+    .sum
+
+  val fancyDotProduct = (vecA zip vecB)
+    .foldLeft(0){ case(acc, ab) => acc + (ab._1 * ab._2) }
+
+
+  // Scala gives you ample opportunity to write unreadable code.
+  // This is not good code!!!
+  val tooFancyDotProduct =
+    (0 /: (vecA zip vecB)){ case(acc, ab) => acc + (ab._1 * ab._2) }
 }

ov0/src/main/scala/oppgavetekst.org

@@ -0,0 +1,44 @@
+* Excercise Zero
+  The goal of this excercise is to gain some familiarity with developing for 
+  FPGAs using chisel. 
+  In this exercise you will implement a circuit capable of performing matrix 
+  matrix multiplication in the chisel hardware description language.
+
+* Matrix matrix multiplication
+  When designing digital logic you should always start with decomposition.
+  Your first task is therefore to implement a dot product calculator, since 
+  a matrix matrix multiplication is essentially a series of these.
+  
+* Dot Product calculator
+  First, let's consider how a dot product calculator would look like in regular
+  scala:
+  
+  #+begin_src scala
+
+    val vecA = List(1,  2, 4)
+    val vecB = List(2, -3, 1)
+
+    val dotProductForLoop = {
+      var dotProduct = 0
+      for(i <- 0 until vecA.length){
+        dotProduct = dotProduct + (vecA(i) * vecB(i))
+      }
+      dotProduct
+    }
+
+    // Scala has rich support for functional programming
+    val dotProductFP = (vecA zip vecB)
+      .map{ case(a, b) => a*b }
+      .sum
+  #+end_src
+
+  In the for loop version you can see how the dot product is sequentially
+  calculated by multiplying vector values of the same indice and summing the
+  result.
+  
+  The dot product for loop works in a similar fashion to your first design, but
+  before you get there some basics are in order.
+  
+* Your first component
+  There are two types of digital components: Combinatorial and stateful.
+  

ov0/test_run_dir/Core.CoreMain1039581728/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain1083714348/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain1235086389/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain1237797471/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain1341624143/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain1384621276/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain1414129309/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain1511946949/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain1700476185/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain1803099112/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain1902845525/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain26358827/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain307141193/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain490998982/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain534289158/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain665881311/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain740971381/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain926682035/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov0/test_run_dir/Core.CoreMain955440956/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov1/build.sbt

@@ -0,0 +1,52 @@
+def scalacOptionsVersion(scalaVersion: String): Seq[String] = {
+  Seq() ++ {
+    // If we're building with Scala > 2.11, enable the compile option
+    //  switch to support our anonymous Bundle definitions:
+    //  https://github.com/scala/bug/issues/10047
+    CrossVersion.partialVersion(scalaVersion) match {
+      case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq()
+      case _ => Seq("-Xsource:2.11")
+    }
+  }
+}
+
+def javacOptionsVersion(scalaVersion: String): Seq[String] = {
+  Seq() ++ {
+    // Scala 2.12 requires Java 8. We continue to generate
+    //  Java 7 compatible code for Scala 2.11
+    //  for compatibility with old clients.
+    CrossVersion.partialVersion(scalaVersion) match {
+      case Some((2, scalaMajor: Long)) if scalaMajor < 12 =>
+        Seq("-source", "1.7", "-target", "1.7")
+      case _ =>
+        Seq("-source", "1.8", "-target", "1.8")
+    }
+  }
+}
+
+name := "chisel-module-template"
+
+version := "3.1.0"
+
+scalaVersion := "2.12.4"
+
+crossScalaVersions := Seq("2.11.12", "2.12.4")
+
+resolvers ++= Seq(
+  Resolver.sonatypeRepo("snapshots"),
+  Resolver.sonatypeRepo("releases")
+)
+
+// Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
+val defaultVersions = Map(
+  "chisel3" -> "3.1.+",
+  "chisel-iotesters" -> "1.2.+"
+  )
+
+libraryDependencies ++= (Seq("chisel3","chisel-iotesters").map {
+  dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) })
+
+scalacOptions ++= scalacOptionsVersion(scalaVersion.value)
+scalacOptions ++= Seq("-language:reflectiveCalls")
+
+javacOptions ++= javacOptionsVersion(scalaVersion.value)

ov1/project/build.properties

@@ -0,0 +1 @@
+sbt.version = 1.1.0

ov1/src/main/scala/Const.scala

@@ -0,0 +1,256 @@
+package Ov1
+
+import chisel3._
+import chisel3.util._
+import chisel3.core.Input
+import chisel3.iotesters.PeekPokeTester
+
+
+object Instructions {
+  def BEQ                = BitPat("b?????????????????000?????1100011")
+  def BNE                = BitPat("b?????????????????001?????1100011")
+  def BLT                = BitPat("b?????????????????100?????1100011")
+  def BGE                = BitPat("b?????????????????101?????1100011")
+  def BLTU               = BitPat("b?????????????????110?????1100011")
+  def BGEU               = BitPat("b?????????????????111?????1100011")
+  def JALR               = BitPat("b?????????????????000?????1100111")
+  def JAL                = BitPat("b?????????????????????????1101111")
+  def LUI                = BitPat("b?????????????????????????0110111")
+  def AUIPC              = BitPat("b?????????????????????????0010111")
+  def ADDI               = BitPat("b?????????????????000?????0010011")
+  def SLLI               = BitPat("b000000???????????001?????0010011")
+  def SLTI               = BitPat("b?????????????????010?????0010011")
+  def SLTIU              = BitPat("b?????????????????011?????0010011")
+  def XORI               = BitPat("b?????????????????100?????0010011")
+  def SRLI               = BitPat("b000000???????????101?????0010011")
+  def SRAI               = BitPat("b010000???????????101?????0010011")
+  def ORI                = BitPat("b?????????????????110?????0010011")
+  def ANDI               = BitPat("b?????????????????111?????0010011")
+  def ADD                = BitPat("b0000000??????????000?????0110011")
+  def SUB                = BitPat("b0100000??????????000?????0110011")
+  def SLL                = BitPat("b0000000??????????001?????0110011")
+  def SLT                = BitPat("b0000000??????????010?????0110011")
+  def SLTU               = BitPat("b0000000??????????011?????0110011")
+  def XOR                = BitPat("b0000000??????????100?????0110011")
+  def SRL                = BitPat("b0000000??????????101?????0110011")
+  def SRA                = BitPat("b0100000??????????101?????0110011")
+  def OR                 = BitPat("b0000000??????????110?????0110011")
+  def AND                = BitPat("b0000000??????????111?????0110011")
+  def ADDIW              = BitPat("b?????????????????000?????0011011")
+  def SLLIW              = BitPat("b0000000??????????001?????0011011")
+  def SRLIW              = BitPat("b0000000??????????101?????0011011")
+  def SRAIW              = BitPat("b0100000??????????101?????0011011")
+  def ADDW               = BitPat("b0000000??????????000?????0111011")
+  def SUBW               = BitPat("b0100000??????????000?????0111011")
+  def SLLW               = BitPat("b0000000??????????001?????0111011")
+  def SRLW               = BitPat("b0000000??????????101?????0111011")
+  def SRAW               = BitPat("b0100000??????????101?????0111011")
+  def LB                 = BitPat("b?????????????????000?????0000011")
+  def LH                 = BitPat("b?????????????????001?????0000011")
+  def LW                 = BitPat("b?????????????????010?????0000011")
+  def LD                 = BitPat("b?????????????????011?????0000011")
+  def LBU                = BitPat("b?????????????????100?????0000011")
+  def LHU                = BitPat("b?????????????????101?????0000011")
+  def LWU                = BitPat("b?????????????????110?????0000011")
+  def SB                 = BitPat("b?????????????????000?????0100011")
+  def SH                 = BitPat("b?????????????????001?????0100011")
+  def SW                 = BitPat("b?????????????????010?????0100011")
+  def SD                 = BitPat("b?????????????????011?????0100011")
+  def FENCE              = BitPat("b?????????????????000?????0001111")
+  def FENCE_I            = BitPat("b?????????????????001?????0001111")
+  def MUL                = BitPat("b0000001??????????000?????0110011")
+  def MULH               = BitPat("b0000001??????????001?????0110011")
+  def MULHSU             = BitPat("b0000001??????????010?????0110011")
+  def MULHU              = BitPat("b0000001??????????011?????0110011")
+  def DIV                = BitPat("b0000001??????????100?????0110011")
+  def DIVU               = BitPat("b0000001??????????101?????0110011")
+  def REM                = BitPat("b0000001??????????110?????0110011")
+  def REMU               = BitPat("b0000001??????????111?????0110011")
+  def MULW               = BitPat("b0000001??????????000?????0111011")
+  def DIVW               = BitPat("b0000001??????????100?????0111011")
+  def DIVUW              = BitPat("b0000001??????????101?????0111011")
+  def REMW               = BitPat("b0000001??????????110?????0111011")
+  def REMUW              = BitPat("b0000001??????????111?????0111011")
+  def LR_W               = BitPat("b00010??00000?????010?????0101111")
+  def SC_W               = BitPat("b00011????????????010?????0101111")
+  def LR_D               = BitPat("b00010??00000?????011?????0101111")
+  def SC_D               = BitPat("b00011????????????011?????0101111")
+  def ECALL              = BitPat("b00000000000000000000000001110011")
+  def EBREAK             = BitPat("b00000000000100000000000001110011")
+  def URET               = BitPat("b00000000001000000000000001110011")
+  def MRET               = BitPat("b00110000001000000000000001110011")
+  def DRET               = BitPat("b01111011001000000000000001110011")
+  def SFENCE_VMA         = BitPat("b0001001??????????000000001110011")
+  def WFI                = BitPat("b00010000010100000000000001110011")
+  def CSRRW              = BitPat("b?????????????????001?????1110011")
+  def CSRRS              = BitPat("b?????????????????010?????1110011")
+  def CSRRC              = BitPat("b?????????????????011?????1110011")
+  def CSRRWI             = BitPat("b?????????????????101?????1110011")
+  def CSRRSI             = BitPat("b?????????????????110?????1110011")
+  def CSRRCI             = BitPat("b?????????????????111?????1110011")
+  def CUSTOM0            = BitPat("b?????????????????000?????0001011")
+  def CUSTOM0_RS1        = BitPat("b?????????????????010?????0001011")
+  def CUSTOM0_RS1_RS2    = BitPat("b?????????????????011?????0001011")
+  def CUSTOM0_RD         = BitPat("b?????????????????100?????0001011")
+  def CUSTOM0_RD_RS1     = BitPat("b?????????????????110?????0001011")
+  def CUSTOM0_RD_RS1_RS2 = BitPat("b?????????????????111?????0001011")
+  def CUSTOM1            = BitPat("b?????????????????000?????0101011")
+  def CUSTOM1_RS1        = BitPat("b?????????????????010?????0101011")
+  def CUSTOM1_RS1_RS2    = BitPat("b?????????????????011?????0101011")
+  def CUSTOM1_RD         = BitPat("b?????????????????100?????0101011")
+  def CUSTOM1_RD_RS1     = BitPat("b?????????????????110?????0101011")
+  def CUSTOM1_RD_RS1_RS2 = BitPat("b?????????????????111?????0101011")
+  def CUSTOM2            = BitPat("b?????????????????000?????1011011")
+  def CUSTOM2_RS1        = BitPat("b?????????????????010?????1011011")
+  def CUSTOM2_RS1_RS2    = BitPat("b?????????????????011?????1011011")
+  def CUSTOM2_RD         = BitPat("b?????????????????100?????1011011")
+  def CUSTOM2_RD_RS1     = BitPat("b?????????????????110?????1011011")
+  def CUSTOM2_RD_RS1_RS2 = BitPat("b?????????????????111?????1011011")
+  def CUSTOM3            = BitPat("b?????????????????000?????1111011")
+  def CUSTOM3_RS1        = BitPat("b?????????????????010?????1111011")
+  def CUSTOM3_RS1_RS2    = BitPat("b?????????????????011?????1111011")
+  def CUSTOM3_RD         = BitPat("b?????????????????100?????1111011")
+  def CUSTOM3_RD_RS1     = BitPat("b?????????????????110?????1111011")
+  def CUSTOM3_RD_RS1_RS2 = BitPat("b?????????????????111?????1111011")
+  def SLLI_RV32          = BitPat("b0000000??????????001?????0010011")
+  def SRLI_RV32          = BitPat("b0000000??????????101?????0010011")
+  def SRAI_RV32          = BitPat("b0100000??????????101?????0010011")
+  def RDCYCLE            = BitPat("b11000000000000000010?????1110011")
+  def RDTIME             = BitPat("b11000000000100000010?????1110011")
+  def RDINSTRET          = BitPat("b11000000001000000010?????1110011")
+  def RDCYCLEH           = BitPat("b11001000000000000010?????1110011")
+  def RDTIMEH            = BitPat("b11001000000100000010?????1110011")
+  def RDINSTRETH         = BitPat("b11001000001000000010?????1110011")
+}
+
+
+object ScalarOpConstants
+{
+   //************************************
+   // Control Signals
+
+   val Y      = true.B
+   val N      = false.B
+
+   // PC Select Signal
+   val PC_4   = 0.asUInt(3.W)  // PC + 4
+   val PC_BR  = 1.asUInt(3.W)  // branch_target
+   val PC_J   = 2.asUInt(3.W)  // jump_target
+   val PC_JR  = 3.asUInt(3.W)  // jump_reg_target
+   val PC_EXC = 4.asUInt(3.W)  // exception
+
+   // Branch Type
+   val BR_N   = 0.asUInt(4.W)  // Next
+   val BR_NE  = 1.asUInt(4.W)  // Branch on NotEqual
+   val BR_EQ  = 2.asUInt(4.W)  // Branch on Equal
+   val BR_GE  = 3.asUInt(4.W)  // Branch on Greater/Equal
+   val BR_GEU = 4.asUInt(4.W)  // Branch on Greater/Equal Unsigned
+   val BR_LT  = 5.asUInt(4.W)  // Branch on Less Than
+   val BR_LTU = 6.asUInt(4.W)  // Branch on Less Than Unsigned
+   val BR_J   = 7.asUInt(4.W)  // Jump
+   val BR_JR  = 8.asUInt(4.W)  // Jump Register
+
+   // RS1 Operand Select Signal
+   val OP1_RS1 = 0.asUInt(2.W) // Register Source #1
+   val OP1_IMU = 1.asUInt(2.W) // immediate, U-type
+   val OP1_IMZ = 2.asUInt(2.W) // Zero-extended rs1 field of inst, for CSRI instructions
+   val OP1_X   = 0.asUInt(2.W)
+
+   // RS2 Operand Select Signal
+   val OP2_RS2 = 0.asUInt(2.W) // Register Source #2
+   val OP2_IMI = 1.asUInt(2.W) // immediate, I-type
+   val OP2_IMS = 2.asUInt(2.W) // immediate, S-type
+   val OP2_PC  = 3.asUInt(2.W) // PC
+   val OP2_X   = 0.asUInt(2.W)
+
+   // Register File Write Enable Signal
+   val REN_0   = false.B
+   val REN_1   = true.B
+   val REN_X   = false.B
+
+   // ALU Operation Signal
+   val ALU_ADD = 1.asUInt(4.W)
+   val ALU_SUB = 2.asUInt(4.W)
+   val ALU_SLL = 3.asUInt(4.W)
+   val ALU_SRL = 4.asUInt(4.W)
+   val ALU_SRA = 5.asUInt(4.W)
+   val ALU_AND = 6.asUInt(4.W)
+   val ALU_OR  = 7.asUInt(4.W)
+   val ALU_XOR = 8.asUInt(4.W)
+   val ALU_SLT = 9.asUInt(4.W)
+   val ALU_SLTU= 10.asUInt(4.W)
+   val ALU_COPY1= 11.asUInt(4.W)
+   val ALU_X   = 0.asUInt(4.W)
+
+   // Writeback Select Signal
+   val WB_ALU  = 0.asUInt(2.W)
+   val WB_MEM  = 1.asUInt(2.W)
+   val WB_PC4  = 2.asUInt(2.W)
+   val WB_CSR  = 3.asUInt(2.W)
+   val WB_X    = 0.asUInt(2.W)
+
+   // Memory Function Type (Read,Write,Fence) Signal
+   val MWR_R   = 0.asUInt(2.W)
+   val MWR_W   = 1.asUInt(2.W)
+   val MWR_F   = 2.asUInt(2.W)
+   val MWR_X   = 0.asUInt(2.W)
+
+   // Memory Enable Signal
+   val MEN_0   = Bool(false)
+   val MEN_1   = Bool(true)
+   val MEN_X   = Bool(false)
+
+   // Memory Mask Type Signal
+   val MSK_B   = 0.asUInt(3.W)
+   val MSK_BU  = 1.asUInt(3.W)
+   val MSK_H   = 2.asUInt(3.W)
+   val MSK_HU  = 3.asUInt(3.W)
+   val MSK_W   = 4.asUInt(3.W)
+   val MSK_X   = 4.asUInt(3.W)
+
+
+   // Cache Flushes & Sync Primitives
+   val M_N      = 0.asUInt(3.W)
+   val M_SI     = 1.asUInt(3.W)   // synch instruction stream
+   val M_SD     = 2.asUInt(3.W)   // synch data stream
+   val M_FA     = 3.asUInt(3.W)   // flush all caches
+   val M_FD     = 4.asUInt(3.W)   // flush data cache
+
+   // Memory Functions (read, write, fence)
+   val MT_READ  = 0.asUInt(2.W)
+   val MT_WRITE = 1.asUInt(2.W)
+   val MT_FENCE = 2.asUInt(2.W)
+
+}
+
+object MemoryOpConstants
+{
+  val MT_X  = 0.asUInt(3.W)
+  val MT_B  = 1.asUInt(3.W)
+  val MT_H  = 2.asUInt(3.W)
+  val MT_W  = 3.asUInt(3.W)
+  val MT_D  = 4.asUInt(3.W)
+  val MT_BU = 5.asUInt(3.W)
+  val MT_HU = 6.asUInt(3.W)
+  val MT_WU = 7.asUInt(3.W)
+
+  val M_X   = "b0".asUInt(1.W)
+  val M_XRD = "b0".asUInt(1.W) // int load
+  val M_XWR = "b1".asUInt(1.W) // int store
+
+  val DPORT = 0
+  val IPORT = 1
+}
+
+object CSR
+{
+  // commands
+  val SZ = 3.W
+  val X = 0.asUInt(SZ)
+  val Nc = 0.asUInt(SZ)
+  val W = 1.asUInt(SZ)
+  val S = 2.asUInt(SZ)
+  val C = 3.asUInt(SZ)
+  val I = 4.asUInt(SZ)
+  val R = 5.asUInt(SZ)
+}

ov1/src/main/scala/Decoder.scala

@@ -0,0 +1,31 @@
+package Ov1
+
+import chisel3._
+import chisel3.core.Input
+import chisel3.iotesters.PeekPokeTester
+
+/**
+  Decoder should read the top 6 bits and output
+
+  Branch
+  MemRead
+  MemtoReg
+  ALUOp
+  memWrite
+  ALUSrc
+  RegWrite
+  */
+
+class ControlSignals extends Bundle(){
+  val Branch   = Output(Bool())
+  val MemRead  = Output(Bool())
+  val MemtoReg = Output(Bool())
+  val MemWrite = Output(Bool())
+  val ALUSrc   = Output(Bool())
+  val RegWrite = Output(Bool())
+
+}
+
+// class myDecoder(val hurr: Int) extends Module {
+
+// }

ov1/src/main/scala/Defs.scala

@@ -0,0 +1,13 @@
+package Ov1
+
+import chisel3._
+import chisel3.core.Input
+import chisel3.iotesters.PeekPokeTester
+
+object Defs {
+
+  class RType extends Bundle {
+
+  }
+
+}

ov1/src/main/scala/Tile.scala

@@ -0,0 +1,122 @@
+package Ov1
+
+import chisel3._
+import chisel3.util._
+import chisel3.core.Input
+import chisel3.iotesters.PeekPokeTester
+
+
+object CoreMain {
+  def main(args: Array[String]): Unit = {
+
+    iotesters.Driver.execute(args, () => new Tile()) {
+      c => new TileTest(c)
+    }
+  }
+}
+
+class Tile() extends Module{
+
+  val io = IO(
+    new Bundle {
+      val instruction = Input(UInt(32.W))
+      val opcode      = Output(UInt(7.W))
+      val immediate   = Output(UInt(12.W))
+    })
+
+  class Itype extends Bundle {
+    val opcode    = UInt(7.W)
+    val rd        = UInt(5.W)
+    val funct3    = UInt(3.W)
+    val rs1       = UInt(5.W)
+    val immediate = UInt(12.W)
+  }
+
+  import Instructions._
+  import ScalarOpConstants._
+  import MemoryOpConstants._
+  import CSR._
+
+  val memes = io.instruction.asTypeOf(new Itype)
+  io.opcode := memes.opcode
+  io.immediate := memes.immediate
+
+  val defaultSignals = List(N, BR_N  , OP1_X  ,  OP2_X  , ALU_X   , WB_X   , REN_0, MEN_0, M_X  , MT_X,  CSR.Nc)
+
+  val ControlSignals = ListLookup(io.instruction,
+                                  defaultSignals,
+               Array(       /* val  |  BR  |  op1   |   op2     |  ALU    |  wb  | rf   | mem  | mem  | mask |  csr  */
+                            /* inst | type |   sel  |    sel    |   fcn   |  sel | wen  |  en  |  wr  | type |  cmd  */
+                  LW      -> List(Y, BR_N  , OP1_RS1, OP2_IMI , ALU_ADD ,  WB_MEM, REN_1, MEN_1, M_XRD, MT_W,  CSR.Nc),
+                  LB      -> List(Y, BR_N  , OP1_RS1, OP2_IMI , ALU_ADD ,  WB_MEM, REN_1, MEN_1, M_XRD, MT_B,  CSR.Nc),
+                  LBU     -> List(Y, BR_N  , OP1_RS1, OP2_IMI , ALU_ADD ,  WB_MEM, REN_1, MEN_1, M_XRD, MT_BU, CSR.Nc),
+                  LH      -> List(Y, BR_N  , OP1_RS1, OP2_IMI , ALU_ADD ,  WB_MEM, REN_1, MEN_1, M_XRD, MT_H,  CSR.Nc),
+                  LHU     -> List(Y, BR_N  , OP1_RS1, OP2_IMI , ALU_ADD ,  WB_MEM, REN_1, MEN_1, M_XRD, MT_HU, CSR.Nc),
+                  SW      -> List(Y, BR_N  , OP1_RS1, OP2_IMS , ALU_ADD ,  WB_X  , REN_0, MEN_1, M_XWR, MT_W,  CSR.Nc),
+                  SB      -> List(Y, BR_N  , OP1_RS1, OP2_IMS , ALU_ADD ,  WB_X  , REN_0, MEN_1, M_XWR, MT_B,  CSR.Nc),
+                  SH      -> List(Y, BR_N  , OP1_RS1, OP2_IMS , ALU_ADD ,  WB_X  , REN_0, MEN_1, M_XWR, MT_H,  CSR.Nc),
+
+                  AUIPC   -> List(Y, BR_N  , OP1_IMU, OP2_PC  , ALU_ADD ,  WB_ALU, REN_1, MEN_0, M_X ,  MT_X,  CSR.Nc),
+                  LUI     -> List(Y, BR_N  , OP1_IMU, OP2_X   , ALU_COPY1, WB_ALU, REN_1, MEN_0, M_X ,  MT_X,  CSR.Nc),
+
+                  ADDI    -> List(Y, BR_N  , OP1_RS1, OP2_IMI , ALU_ADD ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  ANDI    -> List(Y, BR_N  , OP1_RS1, OP2_IMI , ALU_AND ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  ORI     -> List(Y, BR_N  , OP1_RS1, OP2_IMI , ALU_OR  ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  XORI    -> List(Y, BR_N  , OP1_RS1, OP2_IMI , ALU_XOR ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  SLTI    -> List(Y, BR_N  , OP1_RS1, OP2_IMI , ALU_SLT ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  SLTIU   -> List(Y, BR_N  , OP1_RS1, OP2_IMI , ALU_SLTU,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  SLLI    -> List(Y, BR_N  , OP1_RS1, OP2_IMI , ALU_SLL ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  SRAI    -> List(Y, BR_N  , OP1_RS1, OP2_IMI , ALU_SRA ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  SRLI    -> List(Y, BR_N  , OP1_RS1, OP2_IMI , ALU_SRL ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+
+                  SLL     -> List(Y, BR_N  , OP1_RS1, OP2_RS2 , ALU_SLL ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  ADD     -> List(Y, BR_N  , OP1_RS1, OP2_RS2 , ALU_ADD ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  SUB     -> List(Y, BR_N  , OP1_RS1, OP2_RS2 , ALU_SUB ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  SLT     -> List(Y, BR_N  , OP1_RS1, OP2_RS2 , ALU_SLT ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  SLTU    -> List(Y, BR_N  , OP1_RS1, OP2_RS2 , ALU_SLTU,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  AND     -> List(Y, BR_N  , OP1_RS1, OP2_RS2 , ALU_AND ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  OR      -> List(Y, BR_N  , OP1_RS1, OP2_RS2 , ALU_OR  ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  XOR     -> List(Y, BR_N  , OP1_RS1, OP2_RS2 , ALU_XOR ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  SRA     -> List(Y, BR_N  , OP1_RS1, OP2_RS2 , ALU_SRA ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  SRL     -> List(Y, BR_N  , OP1_RS1, OP2_RS2 , ALU_SRL ,  WB_ALU, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+
+                  JAL     -> List(Y, BR_J  , OP1_X  , OP2_X   , ALU_X   ,  WB_PC4, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  JALR    -> List(Y, BR_JR , OP1_RS1, OP2_IMI , ALU_X   ,  WB_PC4, REN_1, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  BEQ     -> List(Y, BR_EQ , OP1_X  , OP2_X   , ALU_X   ,  WB_X  , REN_0, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  BNE     -> List(Y, BR_NE , OP1_X  , OP2_X   , ALU_X   ,  WB_X  , REN_0, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  BGE     -> List(Y, BR_GE , OP1_X  , OP2_X   , ALU_X   ,  WB_X  , REN_0, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  BGEU    -> List(Y, BR_GEU, OP1_X  , OP2_X   , ALU_X   ,  WB_X  , REN_0, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  BLT     -> List(Y, BR_LT , OP1_X  , OP2_X   , ALU_X   ,  WB_X  , REN_0, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  BLTU    -> List(Y, BR_LTU, OP1_X  , OP2_X   , ALU_X   ,  WB_X  , REN_0, MEN_0, M_X  , MT_X,  CSR.Nc),
+
+                  CSRRWI  -> List(Y, BR_N  , OP1_IMZ, OP2_X   , ALU_COPY1, WB_CSR, REN_1, MEN_0, M_X ,  MT_X,  CSR.W),
+                  CSRRSI  -> List(Y, BR_N  , OP1_IMZ, OP2_X   , ALU_COPY1, WB_CSR, REN_1, MEN_0, M_X ,  MT_X,  CSR.S),
+                  CSRRCI  -> List(Y, BR_N  , OP1_IMZ, OP2_X   , ALU_COPY1, WB_CSR, REN_1, MEN_0, M_X ,  MT_X,  CSR.C),
+                  CSRRW   -> List(Y, BR_N  , OP1_RS1, OP2_X   , ALU_COPY1, WB_CSR, REN_1, MEN_0, M_X ,  MT_X,  CSR.W),
+                  CSRRS   -> List(Y, BR_N  , OP1_RS1, OP2_X   , ALU_COPY1, WB_CSR, REN_1, MEN_0, M_X ,  MT_X,  CSR.S),
+                  CSRRC   -> List(Y, BR_N  , OP1_RS1, OP2_X   , ALU_COPY1, WB_CSR, REN_1, MEN_0, M_X ,  MT_X,  CSR.C),
+
+                  ECALL   -> List(Y, BR_N  , OP1_X  , OP2_X  ,  ALU_X    , WB_X  , REN_0, MEN_0, M_X  , MT_X,  CSR.I),
+                  MRET    -> List(Y, BR_N  , OP1_X  , OP2_X  ,  ALU_X    , WB_X  , REN_0, MEN_0, M_X  , MT_X,  CSR.I),
+                  DRET    -> List(Y, BR_N  , OP1_X  , OP2_X  ,  ALU_X    , WB_X  , REN_0, MEN_0, M_X  , MT_X,  CSR.I),
+                  EBREAK  -> List(Y, BR_N  , OP1_X  , OP2_X  ,  ALU_X    , WB_X  , REN_0, MEN_0, M_X  , MT_X,  CSR.I),
+                  WFI     -> List(Y, BR_N  , OP1_X  , OP2_X  ,  ALU_X    , WB_X  , REN_0, MEN_0, M_X  , MT_X,  CSR.Nc), // implemented as a NOP
+
+                  FENCE_I -> List(Y, BR_N  , OP1_X  , OP2_X  ,  ALU_X    , WB_X  , REN_0, MEN_0, M_X  , MT_X,  CSR.Nc),
+                  FENCE   -> List(Y, BR_N  , OP1_X  , OP2_X  ,  ALU_X    , WB_X  , REN_0, MEN_1, M_X  , MT_X,  CSR.Nc)
+                  // we are already sequentially consistent, so no need to honor the fence instruction
+                  ))
+}
+
+class TileTest(c: Tile) extends PeekPokeTester(c) {
+
+  println("yo")
+  step(1)
+  poke(c.io.instruction, 0xAABB)
+  val hurr = peek(c.io.opcode)
+  val durr = peek(c.io.immediate)
+  println(hurr.toString)
+  println(durr.toString)
+  step(1)
+
+}

ov1/test_run_dir/Core.CoreMain1039581728/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov1/test_run_dir/Core.CoreMain1083714348/daisyMultiplier.anno.json

@@ -0,0 +1,3 @@
+[
+  
+]

ov1/test_run_dir/Core.CoreMain1235086389/daisyMultiplier.anno.json

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+[
+  
+]

ov1/test_run_dir/Core.CoreMain1237797471/daisyMultiplier.anno.json

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+[
+  
+]

ov1/test_run_dir/Core.CoreMain1341624143/daisyMultiplier.anno.json

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+[
+  
+]

ov1/test_run_dir/Core.CoreMain1384621276/daisyMultiplier.anno.json

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+[
+  
+]

ov1/test_run_dir/Core.CoreMain1414129309/daisyMultiplier.anno.json

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+[
+  
+]

ov1/test_run_dir/Core.CoreMain1511946949/daisyMultiplier.anno.json

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+[
+  
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ov1/test_run_dir/Core.CoreMain1700476185/daisyMultiplier.anno.json

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+[
+  
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ov1/test_run_dir/Core.CoreMain1803099112/daisyMultiplier.anno.json

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+[
+  
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ov1/test_run_dir/Core.CoreMain1902845525/daisyMultiplier.anno.json

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+[
+  
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ov1/test_run_dir/Core.CoreMain26358827/daisyMultiplier.anno.json

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+[
+  
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ov1/test_run_dir/Core.CoreMain307141193/daisyMultiplier.anno.json

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+[
+  
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+[
+  
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ov1/test_run_dir/Core.CoreMain534289158/daisyMultiplier.anno.json

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+[
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+[
+  
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+[
+  
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+[
+  
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ov1/test_run_dir/Core.CoreMain955440956/daisyMultiplier.anno.json

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+[
+  
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ov1/test_run_dir/Ov1.CoreMain1236591989/Tile.anno.json

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+[
+  
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ov1/test_run_dir/Ov1.CoreMain1250448684/Tile.anno.json

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+[
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ov1/test_run_dir/Ov1.CoreMain1448190335/Tile.anno.json

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+[
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+[
+  
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+[
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+[
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+[
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+[
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+[
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+[
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ov1/test_run_dir/Ov1.CoreMain472595777/Tile.anno.json

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+[
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+[
+  
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ov1/test_run_dir/Ov1.CoreMain523467091/Tile.anno.json

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+[
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ov1/test_run_dir/Ov1.CoreMain656673641/Tile.anno.json

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+[
+  
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ov1/test_run_dir/Ov1.CoreMain728873685/Tile.anno.json

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+[
+  
+]

ov1/test_run_dir/Ov1.CoreMain849836610/Tile.anno.json

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+[
+  
+]