diff --git a/src/main/scala/MatMul.scala b/src/main/scala/MatMul.scala index 84789b7..d69b41b 100644 --- a/src/main/scala/MatMul.scala +++ b/src/main/scala/MatMul.scala @@ -33,12 +33,12 @@ class MatMul(val rowDimsA: Int, val colDimsA: Int) extends MultiIOModule { matrixA.dataIn := 0.U matrixA.rowIdx := 0.U matrixA.colIdx := 0.U - matrixA.readEnable := false.B + matrixA.writeEnable := false.B matrixB.rowIdx := 0.U matrixB.colIdx := 0.U matrixB.dataIn := 0.U - matrixB.readEnable := false.B + matrixB.writeEnable := false.B dotProdCalc.dataInA := 0.U dotProdCalc.dataInB := 0.U diff --git a/src/main/scala/Matrix.scala b/src/main/scala/Matrix.scala index 066213c..126f436 100644 --- a/src/main/scala/Matrix.scala +++ b/src/main/scala/Matrix.scala @@ -9,12 +9,12 @@ class Matrix(val rowsDim: Int, val colsDim: Int) extends Module { val io = IO( new Bundle { - val colIdx = Input(UInt(32.W)) - val rowIdx = Input(UInt(32.W)) - val dataIn = Input(UInt(32.W)) - val readEnable = Input(Bool()) + val colIdx = Input(UInt(32.W)) + val rowIdx = Input(UInt(32.W)) + val dataIn = Input(UInt(32.W)) + val writeEnable = Input(Bool()) - val dataOut = Output(UInt(32.W)) + val dataOut = Output(UInt(32.W)) } ) @@ -28,8 +28,8 @@ class Matrix(val rowsDim: Int, val colsDim: Int) extends Module { // placeholders io.dataOut := 0.U for(ii <- 0 until rowsDim){ - rows(ii).dataIn := 0.U - rows(ii).readEnable := false.B - rows(ii).idx := 0.U + rows(ii).dataIn := 0.U + rows(ii).writeEnable := false.B + rows(ii).idx := 0.U } } diff --git a/src/main/scala/Vector.scala b/src/main/scala/Vector.scala index b4c4b23..10afbc7 100644 --- a/src/main/scala/Vector.scala +++ b/src/main/scala/Vector.scala @@ -9,8 +9,7 @@ class Vector(val elements: Int) extends Module { new Bundle { val idx = Input(UInt(32.W)) val dataIn = Input(UInt(32.W)) - // val writeEnable = Input(Bool()) - val readEnable = Input(Bool()) + val writeEnable = Input(Bool()) val dataOut = Output(UInt(32.W)) } @@ -20,7 +19,7 @@ class Vector(val elements: Int) extends Module { val internalVector = RegInit(VecInit(List.fill(elements)(0.U(32.W)))) - when(io.readEnable){ + when(io.writeEnable){ // TODO: // When writeEnable is true the content of internalVector at the index specified // by idx should be set to the value of io.dataIn diff --git a/src/test/scala/MatrixSpec.scala b/src/test/scala/MatrixSpec.scala index ab81435..c7ff13b 100644 --- a/src/test/scala/MatrixSpec.scala +++ b/src/test/scala/MatrixSpec.scala @@ -24,7 +24,7 @@ class MatrixSpec extends FlatSpec with Matchers { } - it should "Retain its contents when readEnable is low" in { + it should "Retain its contents when writeEnable is low" in { wrapTester( chisel3.iotesters.Driver(() => new Matrix(10,10)) { c => new UpdatesData(c) @@ -41,7 +41,7 @@ object MatrixTests { List.fill(c.rowsDim)(scala.util.Random.nextInt(20) + 1) } - poke(c.io.readEnable, true) + poke(c.io.writeEnable, true) for(col <- 0 until c.colsDim){ for(row <- 0 until c.rowsDim){ poke(c.io.colIdx, col) @@ -68,7 +68,7 @@ object MatrixTests { List.fill(c.rowsDim)(scala.util.Random.nextInt(20) + 1) } - poke(c.io.readEnable, true) + poke(c.io.writeEnable, true) for(col <- 0 until c.colsDim){ for(row <- 0 until c.rowsDim){ poke(c.io.colIdx, col) @@ -78,7 +78,7 @@ object MatrixTests { } } - poke(c.io.readEnable, false) + poke(c.io.writeEnable, false) for(col <- 0 until c.colsDim){ for(row <- 0 until c.rowsDim){ diff --git a/src/test/scala/VectorSpec.scala b/src/test/scala/VectorSpec.scala index 82cb873..c830357 100644 --- a/src/test/scala/VectorSpec.scala +++ b/src/test/scala/VectorSpec.scala @@ -15,39 +15,38 @@ class VectorSpec extends FlatSpec with Matchers { behavior of "Vector" - it should "Not read data when read enable is false" in { - // FileUtils.getSvg("Adder") + it should "Not update its contents when write enable is false" in { wrapTester( chisel3.iotesters.Driver(() => new Vector(elements)) { c => - new ReadEnable(c) + new WriteEnable(c) } should be(true) ) } - // it should "Update its registers when read enable is true" in { - // wrapTester( - // chisel3.iotesters.Driver(() => new Vector(elements)) { c => - // new UpdatesData(c) - // } should be(true) - // ) - // } - - // it should "Retain its data once read enable is set to false" in { - // wrapTester( - // chisel3.iotesters.Driver(() => new Vector(elements)) { c => - // new RetainsData(c) - // } should be(true) - // ) - // } + it should "Update its registers when write enable is true" in { + wrapTester( + chisel3.iotesters.Driver(() => new Vector(elements)) { c => + new UpdatesData(c) + } should be(true) + ) + } + + it should "Retain its data once write enable is set to false" in { + wrapTester( + chisel3.iotesters.Driver(() => new Vector(elements)) { c => + new RetainsData(c) + } should be(true) + ) + } } object VectorTests { - class ReadEnable(c: Vector) extends PeekPokeTester(c) { + class WriteEnable(c: Vector) extends PeekPokeTester(c) { poke(c.io.dataIn, 123) - poke(c.io.readEnable, false) + poke(c.io.writeEnable, false) for(ii <- 0 until c.elements){ poke(c.io.idx, ii) @@ -66,7 +65,7 @@ object VectorTests { class UpdatesData(c: Vector) extends PeekPokeTester(c) { - poke(c.io.readEnable, true) + poke(c.io.writeEnable, true) for(ii <- 0 until c.elements){ poke(c.io.idx, ii) @@ -84,7 +83,7 @@ object VectorTests { class RetainsData(c: Vector) extends PeekPokeTester(c) { - poke(c.io.readEnable, true) + poke(c.io.writeEnable, true) for(ii <- 0 until c.elements){ poke(c.io.idx, ii) @@ -92,7 +91,7 @@ object VectorTests { step(1) } - poke(c.io.readEnable, false) + poke(c.io.writeEnable, false) for(ii <- 0 until c.elements){ poke(c.io.idx, ii)