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diff --git a/hdl.org b/hdl.org
index 385cac4..8fe0d26 100644
--- a/hdl.org
+++ b/hdl.org
@@ -1,3 +1,5 @@
+#+LATEX_HEADER: \usepackage{minted}
+
 * Hardware description languages
   Hardware description languages, HDLs for short, are used to model circuits, typically digital.
   HDLs are *declarative* languages, they describe how the circuit should be constructed.
@@ -20,7 +22,8 @@
   Instead of describing how text should be rendered HDLs describe how wires and components in a 
   circuit should be connected.
   Although we have yet to introduce chisel, let's look at some code for a chisel circuit:
-  It is not necessary to understand what is going on in this code to continue.
+  It is not necessary to understand what is going on in this code to continue. The following code generates
+  the circuit shown in figure [[fig:counter]].
   #+begin_src scala
   class SimpleCounter() extends Module {
     val io = IO(
@@ -36,7 +39,9 @@
   }
   #+end_src
   Just like the HTML describes a document the chisel code describes a simple circuit shown below:
-  #+CAPTION: This is the caption for the next figure link (or table)
+  #+NAME:fig:counter
+  #+ATTR_LaTeX: :height 10cm :placement [H]
+  #+CAPTION:Simple adder circuit generated using the chisel code on the previous page.
   [[./Images/counter.png]]
 
 
@@ -47,8 +52,10 @@
 
   While the path from HTML -> Browser is fairly short it's a lot more involved for hardware description!
   This shouldn't come as a suprise, displaying text is less complex than creating digital circuits.
-  A very simplified version of this is shown here:
-  #+CAPTION: Placeholder graphic
+  A very simplified version of this is shown in figure [[fig:flow]].
+  #+NAME:fig:flow
+  #+CAPTION: Flow using HDL.
+  #+ATTR_LaTeX: :height 5cm :placement [H]
   [[./Images/toolchain1.png]]
  
 
@@ -90,10 +97,11 @@
   "html program", but nonetheless we will refer to a scala program building chisel as chisel programs.
   
   We expand upon our first toolchain description:
-  #+CAPTION: Placeholder graphic
+  #+NAME:fig:chisel_flow
+  #+CAPTION:Toolchain flow using chisel.
   [[./Images/toolchain2.png]]
 
-
+  
 ** Scala -> Chisel Graph Builder
    The starting point, a scala program describing how to build a chisel graph.
    This program is not constrained in any way, it's able to do anything any other scala program does,
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diff --git a/introduction.org b/introduction.org
index 257b35d..786717f 100644
--- a/introduction.org
+++ b/introduction.org
@@ -1,3 +1,4 @@
+#+LATEX_HEADER: \usepackage{minted}
 * Writing chisel
 ** Prerequisites
    + *You should have some idea of how digital logic circuits work.*
@@ -247,7 +248,7 @@
     using testOnly <TAB>
     
     Running the test should look something like this.
-    #+begin_src
+    #+begin_src text
     sbt:chisel-module-template> testOnly Examples.MyIncrementTest
     Run starting. Expected test count is: 0
     ...
@@ -355,7 +356,7 @@
    Which can yield two different circuits depending on the opSel argument:
    True:
    [[./Images/ScalaCond1.png]]
-   #+begin_src
+   #+begin_src text
    .
    .
    .
@@ -591,13 +592,13 @@
     }
     #+end_src
     
-    #+begin_src
+    #+begin_src text
     sbt:chisel-module-template> compile:test
     ...
     #+end_src
     As promised, this code compiles, but when you run the test which actually builds a simulator you
     get the following:
-    #+begin_src
+    #+begin_src text
     [success] Total time: 3 s, completed Apr 25, 2019 3:15:15 PM
     ...
     sbt:chisel-module-template> testOnly Examples.InvalidSpec
@@ -617,7 +618,7 @@
     #+end_src
     
     While scary, the actual error is only this line:
-    #+begin_src
+    #+begin_src text
     firrtl.passes.CheckInitialization$RefNotInitializedException: @[Example.scala 25:21:@20.4] : [module Invalid]  Reference myVec is not fully initialized.
      : myVec.io.idx <= VOID
     #+end_src
@@ -693,7 +694,7 @@
    In order to make it extra clear the Driver has the optional "verbose" parameter set to true.
    This yields the following:
    
-   #+begin_src
+   #+begin_src text
    DelaySpec:
    SimpleDelay
    ...
@@ -819,7 +820,7 @@
     
     As it turns out printf can be rather misleading when using stateful circuits.
     To see this in action, try running ~testOnly Examples.EvilPrintfSpec~ which yields the following
-    #+begin_src
+    #+begin_src text
     In cycle 0 the output of counter is: 0
     according to printf output is: 0
     [info] [0.003] 
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